1. Field of the Invention
The present invention relates to nonvolatile semiconductor memory devices having charge pumps, and more particularly to a nonvolatile semiconductor memory device including means to suppress variation in the load of the charge pump.
2. Description of the Prior Art
A flash memory is conventionally known as an example of a nonvolatile semiconductor memory device. A DINOR (DIvided bit-Line NOR) type flash memory which is one of such flash memories is disclosed in TECHNICAL REPORT OF IEICE, SDM93-24, ICD93-26, pp. 15-20.
In such a DINOR type flash memory, an erased state is where electrons are stored in a floating gate (charge storage electrode). A write (program) state is where electrons are drawn from the floating gate. In other words, an operation opposite to that of the generally known NOR type flash memory is carried out. The time required for an erase operation in an NOR type flash memory is approximately 100 msec.-1 sec., whereas the time required for a write operation in a DINOR type flash memory is as short as approximately 100 .mu.sec.
FIG. 12 is a block diagram showing a structure of such a DINOR type flash memory. The structure and operation of a DINOR type flash memory will be described hereinafter.
Referring to FIG. 12, a memory cell array unit 15 is divided into sectors SE1 and SE2. Memory cell array unit 15 includes select gates SG1 and SG2 corresponding to sectors SE1 and SE2, respectively. Memory cell array unit 15 is formed in a p well region 16.
Two main bit lines MB0 and MB1 are arranged in memory cell array unit 15. Main bit lines MB0 and MB1 are connected to a sense amplifier 3 and a write circuit 4 via Y gate transistors YG0 and YG1 within each Y gate 17.
Two sub bit lines SB01 and SB02 are provided corresponding to main bit line MB0. Two sub bit lines SB11 and SB12 are provided corresponding to main bit line MB1. Word lines WL0 and WL1 are arranged so as to cross sub bit lines SB01 and SB11. Word lines WL2 and WL3 are arranged so as to cross sub bit lines SB02 and SB12.
Memory cells (memory transistors) M00-M03 and M10-M13 are provided at the crossings between sub bit lines SB01, SB02, SB11, and SB12 and word lines WL0-WL3. Memory cells M00, M01, M10, and M11 are included in sector SE1. Memory cells M02, M03, M12, and M13 are included in sectors SE2.
Each memory cell has its gate connected to a corresponding sub bit line, its control gate connected to a corresponding word line, and its source connected to a source line SL.
Select gate SG1 includes select gate transistors SG01 and SG11. Select gate SG2 includes select gate transistors SG02 and SG12. Sub bit lines SB01 and SB02 are connected to main bit line MB0 via select gate transistors SG01 and SG02, respectively. Sub bit lines SB11 and SB12 are connected to main bit line MB1 via select gate transistors SGll and SG12, respectively.
An address buffer 9 receives an externally applied address signal to provide an X address signal to an X decoder 10 and an Y address signal to a Y decoder 8. X decoder 10 responds to an X address signal to select any of the plurality of word lines WL0-WL3. Y decoder 8 responds to a Y address signal to generate a select signal that selects any of the plurality of main bit lines MB0 and MB1.
The Y gate transistors in Y gate 17 respond to respective select signals to connect main bit lines MB0 and MB1 to sense amplifier 3 and write circuit 4. In a readout mode, sense amplifier 3 detects data read out on main bit line MB0 or main bit line MB1 to output the same via data input buffer 2. In a write mode, an externally applied data is provided to write circuit 4 via data input/output buffer 2. Write circuit 4 responds to the data to provide a program voltage to main bit lines MB0 and MB1.
High voltage generation circuits 5 and 6 receive externally applied power supply voltage Vcc (for example 5 V) to generate a high voltage. A negative voltage generation circuit 7 receives externally applied power supply voltage Vcc to generate a negative voltage. A verify voltage generation circuit 11 receives externally applied power supply voltage Vcc to provide a predetermined verify voltage to a selected word line in a verify mode. A well potential generation circuit 12 applies a negative voltage to p well region 16 in an erase mode. A source control circuit 13 provides a negative voltage to source line SL in an erase mode. Select gate decoder 14 responds to a portion of the address signal from address buffer 9 to selectively activate select gates SG1 and SG2.
A write/erase control circuit 1 responds to an externally applied control signal to control the operation of each circuit.
The operation of the DINOR type flash memory of the above-structure will be described hereinafter with reference to Table
TABLE 1 ______________________________________ &lt;1&gt; Applied Voltage in Erase Mode Selected De-selected Sector Applied Voltage Sector Applied Voltage Vd Vcg Vs Vbb Vd Vcg Vs Vbb ______________________________________ OPEN 10 V -8 V -8 V OPEN 0 V -8 V -8 V ______________________________________ Selected De-selected Bit Applied Voltage Bit Applied Voltage Vd Vcg Vs Vbb Vd Vcg Vs Vbb ______________________________________ &lt;2&gt; Applied Voltage in Writing Mode 5 V -8 V OPEN 0 V OPEN 0 V 0 V 0 V &lt;3&gt; Applied Voltage in Readout Mode 1 V 3 V 0 V 0 V OPEN 0 V 0 V 0 V ______________________________________